555 timers, who needs them?
Fig 1 shows a free-running astable to produce a continuous train of pulses. On power up C2 is discharged making the inverter input low. Inverter action makes the output high so that C2 starts to charge through VR2. As C2 charges, the inverter input potential rises. When it reaches the upper trip point of the inverter input, the output changes from high to low. C2 now discharges through VR2 causing the input to the inverter to decrease. When it reaches the lower trip point it is interpreted by IC1b as a logic 0 and the output switches to logic 1, causing C2 to begin charging again. The period of the output waveform is of the order VR2 x C2.
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